1. Field of the Invention
The present invention relates to an overshoot suppression circuit for voltage regulator.
2. Background Art
The following describes a conventional voltage regulator. FIG. 5 is a circuit diagram showing a conventional voltage regulator.
The conventional voltage regulator includes: an error amplification circuit 104; an amplifier 110, bias circuits 108 and 111, a reference voltage circuit 109, PMOS transistors 114 and 105 and resistors 106 and 107.
The PMOS transistor 105 is connected between a power supply terminal 101 and an output terminal 103. The resistors 106 and 107 outputting feedback voltage are connected between the output terminal 103 and a ground terminal 100. The error amplification circuit 104 has an inverting input terminal, to which the reference voltage circuit 109 is connected, a non-inverting terminal, to which the feedback voltage is input, and an output terminal, to which a gate of the PMOS transistor 105 is connected. The bias circuit 108 supplies operating current to the error amplification circuit 104. The PMOS transistor 114 is connected between the power supply terminal 101 and the gate of the PMOS transistor 105. The amplifier 110 has a non-inverting terminal, to which the reference voltage circuit 109 is connected, an inverting terminal, to which the feedback voltage is input and an output terminal connected to a gate of the PMOS transistor 114. The bias circuit 111 supplies operating current to the amplifier 110.
The amplifier 110 compares the input feedback voltage and a reference voltage generated at the reference voltage circuit 109. When the feedback voltage is lower than the reference voltage, the amplifier 110 outputs a Hi signal, thus turning the PMOS transistor 114 OFF. If overshoot generated at the voltage of the output terminal 103 makes the feedback voltage higher than the reference voltage, then the amplifier 110 outputs a Lo signal, thus turning the PMOS transistor 114 ON.
The conventional voltage regulator is operated in this way, thus preventing an increase of the overshoot of the voltage of the output terminal 103 (see Patent Document 1, for example).
[Patent Document 1] Japanese Patent Application Laid-Open No. 2005-301439